Top 5 Schematic Design Errors (Part 1)

Top 5 Schematic Design Errors (Part 1)

With today’s circuit designs getting more and more complex, there is an ever-greater risk of schematic errors passing through the design flow. Have you ever wondered what the most common schematic errors are? As Valydate reviews approximately 15 schematics a month, we decided to share the most common issues we see. Each month Valydate will reveal one of the top 5 schematic design errors and its likely causes.

Error #1: All Inputs (No Drivers) on Net

Definition: The "All Inputs" error occurs when there are multiple inputs on a given net, with no discernible drivers.

Major Causes: This issue can be caused for a variety of different reasons, but the majority and likely causes are:

  1. The simple case of a designer thinking the net is fully connected, when in fact the connection has not been completed.  Connection point indicators are common in CAD tools to assist designers in visually verifying these connections, but they are commonly overlooked when working on large designs.
  2. With net names changing as designers move through various levels of hierarchy and circuit re-use, it gets exponentially more difficult to visually trace signals through a schematic.
  3. FPGA programming not matching the schematic commonly creates an abundance of issues. This mismatch is often caused by lack of collaboration between schematic designers and FPGA programmers.

(To be contined)