Electronic Design Analysis Services

 

Valydate’s electronic design analysis and verification expertise is build up from three main areas of verification:

 

  1. Valydate’s Schematic Integrity Analysis is industry-leading and provides 100% netlist parametric verification. This analysis also identifies poor design practices and offers recommendations to improve clients’ designs.
  2. Complementing Valydate’s Schematic Integrity Analysis™, we also provide advanced Signal Integrity Analysis for both pre- and post-layout. Clients not only receive accurate and comprehensive Signal Integrity Reports but the Valydate team also offers recommendations to resolve any identified issues (removing impedance discontinuities, buffer insertions, driver upsizing, aggressor downsizing, wire shielding, routing changes, etc).
  3. Valydate also provides advanced Static Timing Analysis (STA) for both pre- and post-layout. We not only deliver accurate and comprehensive Static Timing Analysis Reports to our clients, but also offer recommendations to resolve any identified issues (optimizing routing constraints, back-annotation of track delays, tromboning of traces to match timing, etc).

The following table details what is required for each of Valydate’s analysis services.

Information Dependencies for Valydate Analysis (R = Required, D = Desired)

Item Schematic Integrity Signal Integrity Static Timing Details
BoM with Refdes and Manufacturer's Part Numbers R     Perfered that each RefDes is on online line. Simple .text or xls file
Netlist R R R Standard Netlist export Simple .txt
.PDF Schematic R     Text-Searcable version .PDF with RefDes and manufacturer's part numbers
Custom Device Files R R R For each ASIC or Programmable, the Universal Constraints File (UFC) defining pins vs. technology vs. type
Product Spec D D D Helps context if available
HW Block Diagram   R R Showing major buses within the design vs. manufacturer's part number
Board CAD File   R R Example: Allegro .brd file
Board Stackup   R R Defining layers and materials
Schedule R R R Showing target layout start, layout complete and key review dates.
P.O. R R R Prior to work start
Typical Execution 2 wks 2-4 wks 2-4 wks Varies with design complexity

 

Valydate can quote on these services within a maximum of two business days from receipt of key data dependencies. To ease the delivery of this data, Valydate will setup a secure FTP login for your company. Your data never leaves the secure server environment at Valydate, and is never shared outside of the company.

Want to learn more? Have questions? Click here for a free schematic review estimate. Or contact our business manager at 1 613 627 4702 or send an email to info@valydate.com


Testimonials

"Valydates analysis service identified real errors before we committed our design. This helped us get to market faster with a higher quality product."

Ben Brown
VP Engineering, LTX-Credence

“Valydates Schematic Integrity service has been very useful; not only in finding some issues, but also as a thorough check in verifying that other parts of the design have been done correctly.”

Milan Fait, Alcatel-Lucent HW Design

“A must have process before fabrication to avoid unnecessary re-spin”

VP of Digital Hardware Eng., ATE Solutions Provider

“The service provided to us by Valydate helps us reduce the risk of going in layout with a complex design strategic to our companys growth. Some findings in the report will save us precious time in debugging and we are confident that this first layout will even be the version released to production.”

Andre Lessard, Hardware Manager, Commscope