The second day of DesignCon2015 has started. If you haven't had a chance to meet us on the first day, come to booth #953 today and tomorrow for a live demo of one of our newest technologies. Mike and Melissa will be happy to see you!
News & Blog
Altium and Valydate Announce Partnership and Showcase New Powerful Design Analysis and Verification Technology at DesignCon 2015
We’re excited to announce a partnership with Altium to bring the benefits of our ValydateVERA – a new powerful schematic reviewer – to their Altium Designer customers. The strategic alliance will save engineers time and money with in-depth verification as well as the capability to significantly streamline their design cycles.
“VERA has the capability to integrate into Altium Designer and provides a critical advantage by successfully eliminating respins, increasing hardware design time and cost savings and streamlining design cycles,” said Michael Alam, CEO of Valydate. “With our partnership, Altium customers will now have access to the most cost effective method to fully review schematic design.”
Powered by Valydate’s patented verification engine, VERA integrates seamlessly into Altium Designer, providing an invaluable complement to the design process. VERA helps increase customer efficiency by allowing design teams to save hundreds of hours of visual inspection and lab debug time. Customers are able to dramatically reduce design cycles and time-to-market by using VERA to inspect schematics against a predefined list of 100+ checks. These checks take advantage of an extensive intelligent model component library.
“The ValydateVERA design analysis and verification engine is truly innovative and integrates seamlessly into Altium Designer,” said Daniel Fernsebner, Director of Technical Partnerships for Altium. “The partnership with Valydate offers our customers an innovative solution to enhance their competitive advantage through deep verification, leading to a reduction in respins with little to no additional effort from hardware designers.”
Both companies are demonstrating at DesignCon 2015, January 27-29, in Santa Clara. Drop by the Altium Booth #1034 and Valydate Booth#953 for a first hand demonstration.
Valydate Announces ValydateVera™ – A Powerful Design Analysis & Verification Tool which delivers time/cost savings, helping designers to streamline design cycles and eliminate respins.
We’re excited to announce our new powerful schematic reviewer, called ValydateVERA™ (VERA), which will allow our customers to gain in-depth verification with time/cost savings and the capability to significantly streamline their design cycles. As schematics become increasingly complex, proper test and review techniques become even more important. VERA systematically improves the business performance of electronic design teams to gain competitive and faster-to-market advantages.
Powered by Valydate’s patented verification engine, VERA is an invaluable complement to the design process which saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. VERA fully inspects schematics using pre-defined checks and an extensive intelligent model component library.
“VERA has the capability to integrate seamlessly into industry-leading schematic capture tools where clients benefit from the elimination of design errors early in hardware design cycles, when these errors have the least impact on time, quality and cost. Now a critical complement to the design process, VERA is the most cost effective method to fully review schematic design.”
Michael Alam, CEO of Valydate
Proven using hundreds of client designs over the last five years, VERA enables reduced hardware cycles which lead to faster time-to-market; reduction in development; testing and warranty costs; faster integration to high yield manufacturing; improved yield and decreased field returns; and superior product quality.
Take a minute to browse our shiny new website 2.0. Now with 10% more verification than your next leading brand.
Valydate is proud to be nominated as one of the finalists for DesignCon Best in Design & Test Awards this year. The awards recognize top-notch leaders in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity. There are 9 distinct categories of Best in Design & Test Awards: General Purpose Test, Signal Integrity/High-Speed Test, Semiconductor/IP, RF/Microwave Test, Power/Analog Tools, Interconnect Technologies & Components, EMI Design Tools & Test, Design Verification Tools, and Board & System Design & Simulation. Valydate has been chosen as a finalist in the Design Verification Tools category with its Valydate VERA software tool after passing through hundreds of other participants.
Valydate VERA is the first licensable Schematic Integrity Verification tool in the world. It fully inspects 100% of the nets on a schematic using pre-defined checks and an extensive intelligent model component library. With VERA, design teams can save hundreds of hours of visual inspection and lab debug time.
For more information regarding the awards, click here.
Celso Faia – Valydate's top Signal Integrity (SI) and Power Integrity (PI) Verification engineer – has been nominated as a finalist for DesignCon Engineer of the Year 2015 Award. This is a $10,000 award sponsored by National Instruments for the winner to designate to his choice of institution of higher learning.
Celso has supported hundreds of clients with their complex electronic design verifications to insure zero defects and “right first time” board operation. He often develops innovative solutions to resolve complex SI and PI issues. For example, in 2014, many of Valydate’s clients requested SI analysis on designs that contained hundreds and sometimes thousands of high-speed nets. Fully simulating these designs one net at a time is both very time-consuming and cost prohibitive. However, clients still needed 100% netlist verification to insure that their high-speed complex boards were defect free from a SI viewpoint. Celso developed a method to verify and simulate ALL high -peed nets, quickly and cost effectively. This enabled full SI analysis of complex boards, while still meeting end client deadlines and budgets.
The result will be announced at DesignCon 2015 on Wednesday, January 28 at 5:00pm in the ChipHead Theater. So STAY TUNED!
In the meantime, click here for more information regarding the award as well as the voting process.
Valydate thanks the unclear number of participants in Valydate's Cryptography Awareness month.
Valydate’s COO Peter Campbell is officially retiring from active duty. His character and experience will be missed.