News & Blog

Top 5 Schematic Design Errors (Part 2)

With today’s circuit designs getting more and more complex, there is an ever-greater risk of schematic errors passing through the design flow. As a continuation of February's issue, this month Valydate will reveal the second most common schematic design error.

Error #2: The VOIMAX Error.

Definition: A VOIMAX error occurs when the driver output voltage at "Logic High" (VOH) is less than the receiver’s minimum required value of "High-Level Input" (VIH).

Major Causes: 
This issue can be caused for a variety of different reasons, but the more likely causes are:

  1. It's often due to a driver or receiver chip with a broad supply range powered by a supply at a different voltage level than intended. It could be a simple design oversight, possibly when the driver and receiver are several pages apart in the schematic.
  2. It is sometimes unavoidable to have multiple devices communicating at different voltage levels. A designer could be aware of this requirement during the initial design stage, but forget to implement a level translator for the correct voltage thresholds.
  3. There can be nuances of how different devices define their logic thresholds as not all devices follow the JEDEC logic standards. Manufacturers often define their own thresholds differently and the JEDEC logic standards are used as guidelines. These adjusted threshold levels can cause VOIMAX issues between some driver and receiver device pairings.

(To be continued)

Top 5 Schematic Design Errors (Part 1)

With today’s circuit designs getting more and more complex, there is an ever-greater risk of schematic errors passing through the design flow. Have you ever wondered what the most common schematic errors are? As Valydate reviews approximately 15 schematics a month, we decided to share the most common issues we see. Each month Valydate will reveal one of the top 5 schematic design errors and its likely causes.

Error #1: All Inputs (No Drivers) on Net

Definition: The "All Inputs" error occurs when there are multiple inputs on a given net, with no discernible drivers.

Major Causes: This issue can be caused for a variety of different reasons, but the majority and likely causes are:

  1. The simple case of a designer thinking the net is fully connected, when in fact the connection has not been completed.  Connection point indicators are common in CAD tools to assist designers in visually verifying these connections, but they are commonly overlooked when working on large designs.
  2. With net names changing as designers move through various levels of hierarchy and circuit re-use, it gets exponentially more difficult to visually trace signals through a schematic.
  3. FPGA programming not matching the schematic commonly creates an abundance of issues. This mismatch is often caused by lack of collaboration between schematic designers and FPGA programmers.

(To be contined)

Nuvation Partners with Valydate for Signal and Power Integrity Analysis

“Nuvation is a perfect partner for us as we complement their design team with our verification expertise. Valydate verification engineers work closely with Nuvation design engineers to ensure that complex electronic designs are right the first time.”

Mark Cianfaglione, CTO of Valydate

January 30, 2017, Sunnyvale, California. Nuvation Engineering has partnered with Ottawa, Canada-based Valydate to reduce the time and effort required for the signal and power integrity analysis phases of high-speed electronic design projects. “On projects where we’re pushing the boundaries of high-speed design, resolving SI and PI issues can significantly impact costs,” said Michael Hermann, COO and VP Engineering of Nuvation. “Following best practices in electronic design is not always enough and issues left for discovery during the prototyping stage can push out project schedules and increase costs. In these situations, we have Valydate perform the SI and PI analysis in simulation before we begin prototyping. This significantly reduces the need for board re-spins and contributes to Nuvation’s impressive track record of first-time-right designs.”

“Valydate specializes in Schematic Integrity, Signal Integrity and Power Integrity analysis for high-speed board designs”, said Mark Cianfaglione, CTO of Valydate. “We have a team of engineers that are fully focused on design verifications using Valydate’s most advanced techniques. Nuvation is a perfect partner for us as we complement their design team with our verification expertise. Valydate verification engineers work closely with Nuvation design engineers to ensure that complex electronic designs are right the first time”.

The partnership has proven to be of mutual benefit for both companies. While Valydate is able to expand their customer base by providing high quality hardware design verification services, Nuvation is able to leverage Valydate’s services and award-winning design verification tools to deliver first-time right designs more quickly and cost-efficiently.

About Valydate

Valydate Inc. (www.valydate.com) is the leading hardware design verification company that offered the first automated Schematic Integrity Analysis capability. Our patented schematic verification engine provides automated review & inspection of a schematic design, far exceeding human abilities.  Our clients benefit from the elimination of design errors, reduced hardware re-spins, faster time to market and increased product quality, resulting in increased profits.

About Nuvation Engineering

Nuvation Engineering (www.nuvation.com) provides complex electronic product design services to organizations for which quality, performance, and reliability are business-critical requirements. We excel at designing from the ground up, managing product development from initial architecture through design and development, prototyping, and transition to volume production.

 

Valydate Media Contact

Uyen La, Client Relations Coordinator
Valydate Inc.
u.la@valydate.com

Nuvation Media Contact

Joseph Xavier, Director of Marketing
Nuvation Engineering
joseph.xavier@nuvation.com

 

Valydate Won 2016 TMT Technology Awards

In late October 2016, Valydate is honored to be announced as the winner of the 2016 Technology Awards in the Best Design Verification Tools category with its Valydate VERA™.

Over the past couple of decades, technology has changed how the world conducts business across a variety of industries and platforms. Advances in technology have enabled businesses to be more effecient, cost effective, and connected with clients and customers around the globe than ever before. Significant technological changes in the fields of communication and innovation have altered the way the business world consumes and perceives. The 2016 Technology Awards aim to highlight the key players across the technology industry who have provided the world with new and cutting-edge techniques. 

Overcoming many other applicants, Valydate comes out on top in its field with the patented and unique schematic design verification tool VERA.

The full press release can be found here.


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Valydate Exhibiting at the Upcoming Intel SoC FPGA Developer Forum in San Francisco!

Valydate is happy to announce that we will be exhibiting at the Intel SoC FPGA Developer Forum (ISDF16) event on August 18th, 2016 in San Francisco.

The ISDF is an event dedicated to the technology and application of SoC FPGAs in the Internet of Things (IoT), data center and cloud computing, networking and communications, industrial, automotive, and more. It is an opportunity for participants to learn more about hardware acceleration, new development tools and the wide operating system (OS) support available to get products to market quickly.

Visit Valydate's booth at ISDF to see a live demo of our unique and powerful ValydateVERA™ schematic reviewer. We look forward to seeing you there!

ISDF16_Lockup_Vertical_RGB_Blue_WithDate

 

Valydate Exhibiting at CDNLive 2016 in Boston!

Valydate is excited to announce that we will be exhibiting at Cadence User Conference 2016 (CDNLive Boston 2016) on August 31, 2016 at Boston Marriott Burlington. 

CDNLive Boston 2016 is a global technical conference that connects Cadence® technology users to the engineers who develop the solutions and the industry experts who influence market trends. The event enables participants to share best practices on critical design implementation and verification issues, and to discover inspiring new techniques for realizing advanced silicon, SoCs, and systems.

Valydate will be discussing all services that we have to offer and demonstrating our unique software tool ValydateVERA™. Come out to the event and visit our booth for more information. We look forward to seeing you there!

Valydate is Hiring Again!

Due to the huge success of ValydateVERA™ and the rapid expansion of our customer base, Valydate is growing fast and now looking to hire 5 full-time staff with various skills and experiences to accommodate our growth.

  1. A lead hardware engineer would help lead the Valydate hardware verification team and interface with our clients. 
  2. Two hardware analysts are needed to in the analysis of world class complex electronic designs. 
  3. A software developer is responsible for developing VERA, Valydate's patented verification software tool.
  4. An account manager is responsible for managing Valydate's CRM client database, generate sales and bookings as well as interact with clients and Valydate Sales REps and Partner FAE's

Want to know more? Visit our Careers page for full job descriptions.

Valydate Expands Executive Team with New Vice President of Business Development

Industry Veteran To Drive Customer Acquisition For Rapidly Growing ValydateVERA™

Ottawa, Canada – May 12, 2016 – Valydate Inc., the leader in Schematic, Signal and Power Integrity analysis, today announced it has appointed Peter Connolly as the company’s Vice President of Business Development. Mr. Connolly will be responsible for identifying new sources of growth and customer acquisition for Valydate’s new highly acclaimed schematic reviewer, ValydateVERA™ (VERA). VERA delivers time and cost savings, helping designers to streamline design cycles, eliminate respins, and increase electronic design quality.

“Peter’s addition to our leadership team complements the strong management and business development capabilities we have at Valydate,” said Michael Alam, CEO of Valydate. “His wealth of experience will serve us well as we look to create a new and exciting future for Valydate.” Alam added, “Peter is well known in the industry and his significant experience across various markets and unique perspective will enable us to realize our full potential with VERA.”

An industry veteran with over 30 years of business, operations and sales experience working with high tech companies, Mr. Connolly brings substantial experience in business development, strategic partnerships, licensing, and collaborations with a focus on client and partner engagement.

Prior to joining Valydate, Mr. Connolly was Vice President of Business Development at Fidus Systems since 2002. His role included setting the strategic and tactical direction of sales and attaining growth objectives in various markets for engineering design services. His other former roles include VP of Operations, product line management, procurement and software engineering with companies such as, Cemtech and GMSI (Gandalf Mobile Systems Inc).

“I am excited to join Valydate at such an important time for the company,” stated Mr. Connolly. “It’s a great opportunity to join a company that looks for bold ways to improve critical path activities such as schematic design. I look forward to offering great value with VERA for customers and partners.”

About ValydateVERA™

Launched in 2015, ValydateVERA™ is a powerful design analysis and verification tool that saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. Fully inspecting schematics using pre-defined checks and an extensive intelligent model component library, VERA is the most cost effective method to fully review schematic design.

VERA is available now for purchase or licensing opportunities. For more information on VERA and pricing or licensing, please visit http://vera.valydate.com/

About Valydate

Valydate Inc. is a leading Schematic, Signal and Power Integrity analysis company that offers an innovative and automated approach to schematic review and validation. The Company’s patented verification engine provides automated inspection and review beyond human ability. As schematics become increasingly complex, proper test and review techniques become even more important. Proven through use in hundreds of designs over 6 years, clients benefit from the elimination of design errors early in the hardware design cycle, when they have the least impact on time, quality and cost. Valydate’s clients include those in the telecom, defense and aerospace, and photonics sectors.

Founded in 2010, Valydate operates worldwide. For more information, visit www.valydate.com

Valydate, ValydateVERA and their respective logos, are trademarks of Valydate Inc.

 

Editorial Contact

Michael Alam

m.alam@valydate.com

+1.613.619.1100