March 2017

Top 5 Schematic Design Errors (Part 2)

With today’s circuit designs getting more and more complex, there is an ever-greater risk of schematic errors passing through the design flow. As a continuation of February's issue, this month Valydate will reveal the second most common schematic design error.

Error #2: The VOIMAX Error.

Definition: A VOIMAX error occurs when the driver output voltage at "Logic High" (VOH) is less than the receiver’s minimum required value of "High-Level Input" (VIH).

Major Causes: 
This issue can be caused for a variety of different reasons, but the more likely causes are:

  1. It's often due to a driver or receiver chip with a broad supply range powered by a supply at a different voltage level than intended. It could be a simple design oversight, possibly when the driver and receiver are several pages apart in the schematic.
  2. It is sometimes unavoidable to have multiple devices communicating at different voltage levels. A designer could be aware of this requirement during the initial design stage, but forget to implement a level translator for the correct voltage thresholds.
  3. There can be nuances of how different devices define their logic thresholds as not all devices follow the JEDEC logic standards. Manufacturers often define their own thresholds differently and the JEDEC logic standards are used as guidelines. These adjusted threshold levels can cause VOIMAX issues between some driver and receiver device pairings.

(To be continued)

Top 5 Schematic Design Errors (Part 1)

With today’s circuit designs getting more and more complex, there is an ever-greater risk of schematic errors passing through the design flow. Have you ever wondered what the most common schematic errors are? As Valydate reviews approximately 15 schematics a month, we decided to share the most common issues we see. Each month Valydate will reveal one of the top 5 schematic design errors and its likely causes.

Error #1: All Inputs (No Drivers) on Net

Definition: The "All Inputs" error occurs when there are multiple inputs on a given net, with no discernible drivers.

Major Causes: This issue can be caused for a variety of different reasons, but the majority and likely causes are:

  1. The simple case of a designer thinking the net is fully connected, when in fact the connection has not been completed.  Connection point indicators are common in CAD tools to assist designers in visually verifying these connections, but they are commonly overlooked when working on large designs.
  2. With net names changing as designers move through various levels of hierarchy and circuit re-use, it gets exponentially more difficult to visually trace signals through a schematic.
  3. FPGA programming not matching the schematic commonly creates an abundance of issues. This mismatch is often caused by lack of collaboration between schematic designers and FPGA programmers.

(To be contined)