January 2015

Valydate Won DesignCon Best in Design & Test Award!

From January 27 to 30, Mike and Melissa represented Valydate at DesignCon 2015 in Santa Clara. This was also the first time Valydate VERA made its appearance after the announcement on January 26. Valydate's booth was filled with customers, partners, and prospects who were interested in VERA and its features. Especially, at this event, Valydate was announced to be the winner of the Best in Design & Test Awards in the Design Verification Tools category with its Valydate VERA™. The Awards recognize top leaders in terms of innovation, engineering, and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity.

There is still one more day until the event ends. Come to our booth now for a live demo of Valydate VERA™!

For more information about  2015 DesignCon Awards, click here.

 

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Valydate Won DesignCon Best in Design & Test Awards

 

Visit us at DesignCon2015!

The second day of DesignCon2015 has started. If you haven't had a chance to meet us on the first day, come to booth #953 today and tomorrow for a live demo of one of our newest technologies. Mike and Melissa will be happy to see you!

Valydate & Altium Announce Partnership @DesignCon 2015

Altium and Valydate Announce Partnership and Showcase New Powerful Design Analysis and Verification Technology at DesignCon 2015

We’re excited to announce a partnership with Altium to bring the benefits of our ValydateVERA – a new powerful schematic reviewer – to their Altium Designer customers.  The strategic alliance will save engineers time and money with in-depth verification as well as the capability to significantly streamline their design cycles.

“VERA has the capability to integrate into Altium Designer and provides a critical advantage by successfully eliminating respins, increasing hardware design time and cost savings and streamlining design cycles,” said Michael Alam, CEO of Valydate. “With our partnership, Altium customers will now have access to the most cost effective method to fully review schematic design.”

Powered by Valydate’s patented verification engine, VERA integrates seamlessly into Altium Designer, providing an invaluable complement to the design process. VERA helps increase customer efficiency by allowing design teams to save hundreds of hours of visual inspection and lab debug time. Customers are able to dramatically reduce design cycles and time-to-market by using VERA to inspect schematics against a predefined list of 100+ checks. These checks take advantage of an extensive intelligent model component library.

“The ValydateVERA design analysis and verification engine is truly innovative and integrates seamlessly into Altium Designer,” said Daniel Fernsebner, Director of Technical Partnerships for Altium. “The partnership with Valydate offers our customers an innovative solution to enhance their competitive advantage through deep verification, leading to a reduction in respins with little to no additional effort from hardware designers.”

Both companies are demonstrating at DesignCon 2015, January 27-29, in Santa Clara. Drop by the Altium Booth #1034 and Valydate Booth#953 for a first hand demonstration.

Valydate Announces Powerful Design Analysis and Verification Technology

Valydate Announces ValydateVera™ – A Powerful Design Analysis & Verification Tool which delivers time/cost savings, helping designers to streamline design cycles and eliminate respins.

We’re excited to announce our new powerful schematic reviewer, called ValydateVERA™ (VERA), which will allow our customers to gain in-depth verification with time/cost savings and the capability to significantly streamline their design cycles. As schematics become increasingly complex, proper test and review techniques become even more important. VERA systematically improves the business performance of electronic design teams to gain competitive and faster-to-market advantages.

Powered by Valydate’s patented verification engine, VERA is an invaluable complement to the design process which saves design teams hundreds of hours of visual inspection and lab debug time by automating 100+ proprietary checks for each net within a schematic. VERA fully inspects schematics using pre-defined checks and an extensive intelligent model component library.

“VERA has the capability to integrate seamlessly into industry-leading schematic capture tools where clients benefit from the elimination of design errors early in hardware design cycles, when these errors have the least impact on time, quality and cost. Now a critical complement to the design process, VERA is the most cost effective method to fully review schematic design.”

Michael Alam, CEO of Valydate

Proven using hundreds of client designs over the last five years, VERA enables reduced hardware cycles which lead to faster time-to-market; reduction in development; testing and warranty costs; faster integration to high yield manufacturing; improved yield and decreased field returns; and superior product quality.

To learn more about VERA’s features, benefits and to GET A FREE TRIAL, check out our VERA page