December 2014

DesignCon Best in Design & Test Awards Finalist

Valydate is proud to be nominated as one of the finalists for DesignCon Best in Design & Test Awards this year. The awards recognize top-notch leaders in engineering and new product advancements at the chip, board, or system level, with a special emphasis on signal integrity and power integrity. There are 9 distinct categories of Best in Design & Test Awards: General Purpose Test, Signal Integrity/High-Speed Test, Semiconductor/IP, RF/Microwave Test, Power/Analog Tools, Interconnect Technologies & Components, EMI Design Tools & Test, Design Verification Tools, and Board & System Design & Simulation. Valydate has been chosen as a finalist in the Design Verification Tools category with its Valydate VERA software tool after passing through hundreds of other participants.

Valydate VERA is the first licensable Schematic Integrity Verification tool in the world. It fully inspects 100% of the nets on a schematic using pre-defined checks and an extensive intelligent model component library. With VERA, design teams can save hundreds of hours of visual inspection and lab debug time.  

For more information regarding the awards, click here

Celso Faia Named 2015 Engineer of the Year Finalist!!!

Celso Faia – Valydate's top Signal Integrity (SI) and Power Integrity (PI) Verification engineer – has been nominated as a finalist for DesignCon Engineer of the Year 2015 Award. This is a $10,000 award sponsored by National Instruments for the winner to designate to his choice of institution of higher learning.

Celso has supported hundreds of clients with their complex electronic design verifications to insure zero defects and “right first time” board operation. He often develops innovative solutions to resolve complex SI and PI issues. For example, in 2014, many of Valydate’s clients requested SI analysis on designs that contained hundreds and sometimes thousands of high-speed nets. Fully simulating these designs one net at a time is both very time-consuming and cost prohibitive. However, clients still needed 100% netlist verification to insure that their high-speed complex boards were defect free from a SI viewpoint. Celso developed a method to verify and simulate ALL high -peed nets, quickly and cost effectively. This enabled full SI analysis of complex boards, while still meeting end client deadlines and budgets.

The result will be announced at DesignCon 2015 on Wednesday, January 28 at 5:00pm in the ChipHead Theater. So STAY TUNED!

In the meantime, click here for more information regarding the award as well as the voting process.